1. Field of the Invention
The present invention relates to an integrated circuit structure and a method of fabricating the same, and more particularly, to a semiconductor device and a fabricating method thereof.
2. Description of Related Art
As development in electronic device technology such as communication devices advances, the operating speed of the transistor is getting faster and faster. However, the speed range of the transistor is also limited by the moving speed of electrons and holes in silicon channels.
A method of increasing the operating speed of the transistor is to change the moving speed of electrons and holes in the channel through controlling the mechanical-stress in the channel. Taking a P-type channel metal oxide semiconductor (PMOS) as an example, in the prior art exists a technology of fabricating a source or drain region of the transistor mainly with a material such as SiGe epitaxy. Compared with the characteristics of silicon, since Ge has a larger atom volume and applies a compression stress on the channel, the holes in the source or drain region mainly constituted by SiGe may have a higher mobility and the performance of the device is thus enhanced.
The technology of fabricating the source or drain region of the transistor mainly using a material such as SiGe epitaxy includes removing a portion of a substrate where the source or drain region is predetermined to form. Afterwards, SiGe is filled back in the source or drain region by a selective area epitaxy growth process.
Nevertheless, during a typical process of fabricating a metal oxide semiconductor (MOS), due to considerations of different design requirements, usually channels of a plurality of transistors would have identical channel lengths but the source or drain regions of the transistors have different widths along a channel length direction. Hence, the method of completely filling SiGe into the portion of the substrate predetermined to form the source or drain region would generate different compression stresses in channel regions of the transistors respectively.
Further, when the predetermined portion where the source or drain regions are formed in the substrate is removed by an etching process, due to the loading effect of the etching process, if etched areas have different sizes, the larger area is usually etched faster and more deeply, and a profile thereof is oblique. Thus, strains of the transistors are even more uneven. Consequently, each of the transistors has different performance and reduces the reliability of the semiconductor device.